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advance pr o duct information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2001 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com cs44210 digital pwm controller with headphone monitor features l u p to 1 00 db d y na m i c r ange l 2.4 v to 5.0 v supply l sample rates up to 96 khz l digital tone control ? 3 selectable hpf and lpf corner frequencies ? 12 db boost for bass and treble - 1 db step size l programmable digital volume control ? +18 to -96 db in 1 db steps l peak signal soft limiting l de-emphasis for 32 khz, 44.1 khz, and 48 khz l selectable outputs for each channel including ? channel a: r, l, mono (l + r) / 2, mute ? channel b: r, l, mono (l + r) / 2, mute l pwm popguard ? description the cs44210 is a complete stereo digital-to-pwm class d au- dio amplifier system controller including interpolation, volume control, half bridge pwm driver outputs, and an integrated cs44l10 headphone amplifier in a 24-pin tssop package. the cs44210 architecture uses a direct-to-digital approach that maintains digital signal integrity to the final output filter. this minimizes analog interference effects that can negatively affect system performance. the cs44210 contains on-chip digital bass and treble boost, peak signal limiting, and de-emphasis. the pwm amplifier can achieve greater than 90% efficiency. this efficiency leads to longer battery life for portable systems, smaller device pack- age, less heat sink requirements, and smaller power supplies. the cs44210 provides all the controls necessary to drive high- er voltage output stages for increased power levels. the cs44210 is ideal for integrated, mult-function systems such as shelf-top audio systems, audio mini systems, audio video receivers (avr), boom boxes and powered speakers. ordering information CS44210-KZ -10 to 70 c 24-pin tssop m u l t i b it ds modulator with correction m u l t i b it ds modulator with correction digital volume control, bass/treble boost, compression limiting, de-emphasis control port scl/cclk/dif0 mclk input mux and serial port sda/cdin/dem vl pw m conversion pw m conversion sync_clk driver_b hp_b va_hpb gnd_hpb level shifter va_hpa level shifter hp_a gnd_hpa rst interpolation ad1/cdout tstin sclk lrck input sampling rate lrclk/mclk ratio ad0/cs/dif1 sdin1 sdin2 sdin3 driver_a vd gnd may ? 01 ds539pp1
cs44210 2 ds539pp1 table of contents 1. characteristics and specifications ........................................................................ 4 2. typical connection diagram ...................................................................................... 11 3. register quick reference ...................................................................................... 13 4. register descriptions .................................................................................................. 14 5. pin description ........................................................................................................... ...... 27 6. applications ............................................................................................................. ........ 29 6.1 grounding and power supply decoupling ...................................................................... 29 6.2 clock modes .............................................................................................................. ..... 29 6.3 de-emphasis .............................................................................................................. .... 29 6.4 pwm popguard transient control ................................................................................. 29 6.5 recommended power-up sequence .............................................................................. 30 6.5.1 stand alone mode ................................................................................................ 30 6.5.2 control port mode ................................................................................................ 30 7. control port interface .............................................................................................. 31 7.1 format selection ......................................................................................................... .... 31 7.2 two-wire format .......................................................................................................... .. 31 7.2.1 writing in two-wire format ................................................................................. 31 7.2.2 reading in two-wire format ............................................................................... 31 7.3 spi format ............................................................................................................... ....... 31 7.3.1 writing in spi ....................................................................................................... 31 7.3.2 reading in spi ..................................................................................................... 33 7.4 memory address pointer (map) ................................................................................... 33 7.4.1 incr (auto map increment enable) .................................................................... 33 7.4.2 map3-0 (memory address pointer) ..................................................................... 33 8. parameter definitions .................................................................................................. 36 9. package dimensions ....................................................................................................... 3 7 list of figures figure 1. serial audio data interface timing .................................................................................. 7 figure 2. control port timing - two-wire format ........................................................................... 9 figure 3. control port timing - spi format................................................................................... 10 figure 4. typical cs44210 connection diagram stand-alone mode ........................................... 11 figure 5. typical cs44210 connection diagram control port mode............................................ 12 figure 6. dynamics control block diagram .................................................................................. 21 figure 7. de-emphasis curve .................................................................................................... ... 24 figure 8. control port timing, two-wire format .......................................................................... 32 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi d ed ? as is ? without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before pla cing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of o rder acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. no responsibility is assumed by cirrus logic, inc. f or the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and by furnishing this information, cirrus logic, inc. grants no license, express or implied un der any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of cirrus logic, inc. cirrus logic, inc., copyrigh t owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to cirrus log ic integrated circuits or other parts of cirrus logic, inc. the same consent is given for similar information contained on any cirrus logic website or disk. this c onsent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. the names of products of cirrus logic, inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners wh ich may be registered in some jurisdictions. a list of cirrus logic, inc. trademarks and service marks can be found at http://www.cirrus.com .
cs44210 ds539pp1 3 figure 9. control port timing, spi format (write) ........................................................................ 32 figure 10. control port timing, spi format (read)...................................................................... 33 figure 11. single speed stopband rejection ............................................................................... 34 figure 12. single speed transition band ..................................................................................... 34 figure 13. single speed transition band (detail)......................................................................... 34 figure 14. single speed passband ripple ................................................................................... 34 figure 15. double speed stopband rejection.............................................................................. 34 figure 16. double speed transition band .................................................................................... 34 figure 17. double speed transition band (detail) ....................................................................... 35 figure 18. double speed passband ripple .................................................................................. 35 figure 19. left justified, up to 24-bit data................................................................................... .35 figure 20. right justified, 24-bit data ....................................................................................... .. 35 figure 21. i2s, up to 24-bit data ............................................................................................. .... 35 figure 22. right justified, 16-bit data ........................................................................................ .. 36 list of tables table 1. register quick reference ............................................................................................. .13 table 2. example volume settings .............................................................................................. 16 table 3. example bass boost settings ........................................................................................ 16 table 4. example treble boost settings ...................................................................................... 16 table 5. base boost corner frequencies in single speed mode ................................................ 17 table 6. base boost corner frequencies in double speed mode .............................................. 17 table 7. treble boost corner frequencies in single speed mode .............................................. 18 table 8. example limiter attack rate settings ............................................................................ 19 table 9. example limiter release rate settings ......................................................................... 19 table 10. atapi decode ........................................................................................................ ..... 21 table 11. single speed clock modes - control port mode .......................................................... 23 table 12. single speed clock modes - stand-alone mode ......................................................... 23 table 13. double speed clock modes - control port mode ........................................................ 24 table 14. double speed clock modes - stand-alone mode ........................................................ 24 table 15. digital interface format - dif1 and dif0 (stand-alone mode) .................................... 28
cs44210 4 ds539pp1 1. characteristics and specifications (t a = 25 c; gnd = 0 v; logic "1" = vl = 2.4 v; logic "0" = gnd = 0 v; full-scale output sine wave, 997 hz, mclk = 12.288 mhz, measurement bandwidth 10 hz to 20 khz, unless otherwise specified; fs for single speed mode = 48 khz, sclk = 3.072 mhz; fs for double speed mode = 96 khz, sclk = 6.144 mhz. test load r l =16 ? , c l = 10pf.) (see typical cs44210 connection diagram.) parameter symbol min typ max unit headphone output dynamic performance for vd = vl = va_hpx = 2.4 v dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted tbd tbd - - 93 91 91 89 - - - - db db db db total harmonic distortion + noise 0 dbfs -20 dbfs -60 dbfs thd+n - - - -62 -71 -31 tbd - - db db db interchannel isolation (1 khz) -tbd-db headphone output dynamic performance for vd = vl = va_hpx = 3.0 v dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted tbd tbd - - 95 92 92 90 - - - - db db db db total harmonic distortion + noise 0 db -20 db -60 db thd+n - - - -64 -72 -32 tbd - - db db db interchannel isolation (1 khz) -tbd-db headphone output dynamic performance for vd = vl = va_hpx = 5.0 v dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted tbd tbd - - 99 96 91 93 - - - - db db db db total harmonic distortion + noise 0 db -20 db -60 db thd+n - - - -67 -76 -36 tbd - - db db db interchannel isolation (1 khz) -tbd-db
cs44210 ds539pp1 5 characteristics and specifications (continued) note: 1. filter response is not tested but is guaranteed by design. 2. response is clock dependent and will scale with fs. note that the response plots (figures 11-18) have been normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. 3. referenced to a 1 khz, full-scale sine wave. 4. for single speed mode, the measurement bandwidth is 0.5465 fs to 3 fs. for double speed mode, the measurement bandwidth is 0.577 fs to 1.4 fs. 5. de-emphasis is not available in double speed mode. parameters symbol min typ max units pwm headphone output full scale headphone output voltage tbd 0.85 x va_hp tbd vp headphone output quiescent voltage -0.5 x va_hp- vdc interchannel gain mismatch -0.1-db modulation index --85% maximum headphone output va_hpx=2.4v ac-current va_hpx=5.0v i hp - - 45 80 - - ma ma parameter single speed mode double speed mode symbol min typ max min typ max unit digital filter response (note 1) passband to -0.05 db corner (note 2) to -0.1 db corner to -3 db corner 0 - 0 - - - .4535 - .4998 - 0 0 - - - - .4426 .4984 fs fs fs frequency response 10 hz to 20 khz (note 3) -.02 - +.08 0 - +0.11 db stopband .5465 - - .577 - - fs stopband attenuation (note 4) 50 - - 55 - - db group delay tgd - 9/fs - - 4/fs - s passband group delay deviation 0 - 40 khz 0 - 20 khz - - - 0.36/fs - - - - 1.39/fs 0.23/fs - - s s de-emphasis error fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - +.2/-.1 +.05/-.14 +0/-.22 (note 5) db db db
cs44210 6 ds539pp1 absolute maximum ratings (gnd = 0v; all voltages with respect to ground.) caution: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (gnd = 0v; all voltages with respect to ground.) switching characteristics (t a = -10 to 70 c; vl = 2.4v - 5.0v; inputs: logic 0 = gnd, logic 1 = vl, cl = 20pf) parameters symbol min max units dc power supplies: headphone interface digital va_hpx vl vd 2.4 2.4 2.4 5.5 5.5 5.5 v v v input current, any pin except supplies i in 10 ma digital input voltage v ind -0.3 vl + 0.4 v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c parameters symbol min typ max units ambient temperature t a -10 - 70 c dc power supplies: headphone interface digital va_hpx vl vd 2.4 2.4 2.4 - - - 5.0 5.0 5.0 v v v parameters symbol min typ max units input sample rate single speed mode double speed mode fs fs 8 50 - - 50 100 khz khz mclk duty cycle 40 50 60 % lrck duty cycle 40 50 60 % sclk pulse width low t sclkl 20 - - ns sclk pulse width high t sclkh 20 - - ns sclk period single speed mode t sclkw --ns double speed mode t sclkw --ns sclk rising to lrck edge delay t slrd 20 - - ns sclk rising to lrck edge setup time t slrs 20 - - ns sdin valid to sclk rising setup time t sdlrs 20 - - ns sclk rising to sdin hold time t sdh 20 - - ns 1 128 () fs ---------------------- 1 64 () fs ------------------ -
cs44210 ds539pp1 7 power and thermal characteristics (gnd = 0 v; all voltages with respect to ground. all measurements taken with all zeros input and open outputs, unless otherwise specified.) note: 6. power down mode is defined as rst = lo with all clocks and data lines held static. parameters symbol min typ max units power supplies power supply current- va_hpx= 2.4 v normal operation vd = 2.4 v vl= 2.4 v i va_hp i d i l - - - 1 10 1 - - - ma ma ma power supply current- va_hpx = 2.4v power down mode (note 6) vd = 2.4v vl = 2.4v i va_hp i d i l - - - tbd tbd tbd - - - a a a power supply current- va_hpx = 5.0 v normal operation vd = 5.0 v vl = 5.0 v i va_hp i d i l - - - 2 20 2 - - - ma ma ma power supply current- va_hpx = 5.0v power down mode (note 6) vd = 5.0v vl = 5.0 v i va_hp i d i l - - - tbd tbd tbd - - - a a a total power dissipation- all supplies = 2.4 v normal operation all supplies = 5.0 v - - 29 120 - - mw mw power supply rejection ratio psrr - 0 - db maximum headphone power dissipation va=2.4 v (1 khz full-scale sine wave into 16 ohm load) va=5.0 v - - 23 100 - - mw mw package thermal resistance ja -75- c/watt sclkh t slrs t slrd t sdlrs t sdh t sclkl t sdata sclk lrck sclkw t figure 1. serial audio data interface timing
cs44210 8 ds539pp1 digital characteristics (t a = 25 c; vl = 2.4v - 3.6v; gnd=0v) switching characteristics- control port- two-wire format (note 8) (t a =25 c; vl = 2.4 v - 5.0 v; inputs: logic 0 = gnd, logic 1 = vl, c l =30pf) note: 7. v oh and v ol are tested at an output current of tbd ma. 8. the two-wire format is compatible with the i 2 c protocol. 9. data must be held for sufficient time to bridge the transition time, t fc , of scl. 10. the acknowledge delay is based on mclk and can limit the maximum transaction speed. 11. for single-speed mode and for double-speed mode. parameters symbol min typ max units high-level input voltage v ih 0.7 x vl - - v low-level input voltage v il --0.3 x vlv input leakage current i in --10 a input capacitance -8-pf high-level output voltage (pin 15) (note 7) v oh 0.7 x vl - - v low-level output voltage (pin 15) (note 7) v ol --0.3 x vlv high-level output voltage (pins 11, 13, 14) (note 7) v oh 0.7 x vd - - v low-level output voltage (pins 11, 13, 14) (note 7) v ol - - 0.3 x vd v parameter symbol min max unit scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 9) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc , t rc -1s fall time scl and sda t fc , t fc - 300 ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling (note 10) t ack - (note 11) ns 5 256 fs -------------------- - 5 128 fs ---------------------
cs44210 ds539pp1 9 t buf t hdst t low t hdd t high t sud stop s t a rt sda scl t irs rst t hdst t rc t fc t sust t susp start stop repeated t rd t fd t ack figure 2. control port timing - two-wire format
cs44210 10 ds539pp1 switching characteristics - control port - spi format (t a =25 c; vl = 2.4 v - 5.0 v; inputs: logic 0 = gnd, logic 1 = vl, c l =30pf) note: 12. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 13. data must be held for sufficient time to bridge the transition time of cclk. 14. for f sck < 1 mhz. 15. cdout should not be sampled during this time period. 16. this time is not tested but is guaranteed by design. parameter symbol min max unit cclk clock frequency f sclk -6mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 12) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 13) t dh 15 - ns rise time of cclk and cdin (note 14) t r2 - 100 ns fall time of cclk and cdin (note 15) t f2 - 100 ns transition time from cclk to cdout valid (note 15) t scdov -40ns time from cs rising to cdout high-z (note 16) t cscdo -20ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst cdout t scdov t scdov t cscdo tri-state figure 3. control port timing - spi format
cs44210 ds539pp1 11 2. typical connection diagrams mclk lrck sc l k sdin1 rst va_hpb cs44210 2.4 to 5.0 v supply 100 f + va_hpa supply 1.0 f + vl 19 20 8 7 2 5 3 18 2 1 16 1 9 4 15 14 2. 4 to 5.0 v supply 1.0 f + vd 6 2.4 to 5.0 v 24 sdin2 sdin3 ad1/cdout 23 10 driver_a 17 22 0.15 f 0.15 f 16 ? headphones gnd gnd gnd 0.1 f digital a udio source d if dif 0 1 dem 0.1 f 0.1 f mode control hp _a hp _b tstin 12 11 sync_clk sync clock 13 driver_b output filter output filter 220 f 100 h 220 f 100 h cout + + cout mosfet driver & power stage mosfet driver & power stage * * * this feature is unavailable in this mode. this pin should be grounded. figure 4. typical cs44210 connection diagram stand-alone mode
cs44210 12 ds539pp1 mclk lrck sc l k sdin1 rst va_hpb cs44210 2.4 to 5.0 v supply 100 f + va_hpa supply 1.0 f + vl 19 20 8 7 2 5 3 18 2 1 16 1 9 4 15 14 2.4to5.0v supply 1.0 f + vd 6 2.4 to 5.0 v 24 sdin2 * sdin3 * ad1/cdout 23 10 driver_a 17 22 0.15 f 0.15 f 16 ? headphones g nd gnd gnd 0.1 f ad0/cs scl/cclk sda/cdin 0.1 f 0.1 f hp _a hp _b tstin 12 11 sync_clk sync clock 13 driver_b output filter output filter 220 f 100 h 220 f 100 h cout + + cout mosfet driver & power stage mosfet driver & power stage * unused sdin pins should be connected to gnd digital a udio source c/ mode control figure 5. typical cs44210 connection diagram control port mode
cs44210 ds539pp1 13 3. register quick reference addr function 7 6 5 4 3 2 1 0 2h power and muting control szc1 szc0 pdn flt rupbyp rdnbyp reserved reserved default10100000 3h channel a volume control vola7 vola6 vola5 vola4 vola3 vola2 vola1 vola0 default00000000 4h channel b volume control volb7 volb6 volb5 volb4 volb3 volb2 volb1 volb0 default00000000 5h tone control bb3 bb2 bb1 bb0 tb3 tb2 tb1 tb0 default00000000 6h mode control 1 bbcf1 bbcf0 tbcf1 tbcf0 tc1 tc0 tc_en lim_en default00000000 7h limiter attack rate arate7 arate6 arate5 arate4 arate3 arate2 arate1 arate0 default00010000 8h limiter release rate rrate7 rrate6 rrate5 rrate4 rrate3 rrate2 rrate1 rrate0 default00100000 9h volume and mixing control is1 is0 rmp_sp1 rmp_sp0 atapi3 atapi2 atapi1 atapi0 default00011001 ah mode control2 mclkdiv clkdv1 clkdv0 dbs frqsft1 frqsft0 dem1 dem0 default00000000 bh mode control 3 dif1 dif0 a=b vcbyp cp_en freeze reserved reserved default00000000 ch revision indicator reserved reserved reserved reserved rev3 rev2 rev1 rev0 default 0 0 0 0 read only read only read only read only table 1. register quick reference
cs44210 14 ds539pp1 4. register descriptions 4.1 power and muting control (address 02h) 4.1.1 soft ramp and zero cross control (szc) default = 10 00 - immediate change 01 - zero cross control 10 - ramped control 11 - reserved function: immediate change when immediate change is selected, all level changes will take effect immediately in one step. zero cross control zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. the requested level change will occur after a time-out period of 512 sample periods (10.7 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. ramped control soft ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp- ing, in 1/8 db steps, from the current level to the new level at a rate of 1 db per 8 left/right clock periods. note: ramped control is not available in double speed mode. 4.1.2 power down (pdn) default = 1 0 - disabled 1 - enabled function: the entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. the power-down bit defaults to ? enabled ? on power-up and must be disabled before normal operation in control port mode can occur. 76543210 szc1 szc0 pdn flt rupbyp rdnbyp reserved reserved 10100000
cs44210 ds539pp1 15 4.1.3 float output (flt) default = 0 0 - disabled 1 - enabled function: when enabled, this bit will cause the headphone output of the cs44210 to float when in the power down state (pdn=1). the float function can be used in single-ended applications to maintain the charge on the dc-blocking capacitor during power transients. on power transitions, the output will quickly change to the bias point, however, if the dc-blocking capacitor still has a full charge, as in short power cycles, the tran- sition will be very small, often inaudible. refer to section 6.4 . 4.1.4 ramp up bypass (rupbyp) default = 0 0 - normal 1 - bypass function: when in normal mode, the duty cycle of the output pwm signal is increased at a rate determined by the ramp speed variable (rmp_spx). normal mode is used in single ended applications to reduce pops in the output caused by the dc-blocking capacitor. when the ramp up function is bypassed in single ended applications, there will be an abrupt change in the output signal. refer to section 6.4. 4.1.5 ramp down bypass (rdnbyp) default = 0 0 - disabled 1 - enabled function: when in normal mode, the duty cycle of the output pwm signal is decreased at a rate determined by the ramp speed variable (rmp_spx). normal mode is used in single ended applications to reduce pops in the output caused by the dc-blocking capacitor and changes in bias conditions. when the ramp down function is bypassed in single ended applications, there will be an abrupt change in the output signal. re- fer to section 6.4. 4.2 channel a volume control (address 03h) (vola) 4.3 channel b volume control (address 04h) (volb) default = 0 db (no attenuation) function: the volume control registers allow independent control of the signal levels in 1 db increments from +18 to -96 db. volume settings are decoded using a 2 ? s complement code, as shown in table 2. the volume changes are implemented as dictated by the soft and zero cross bits. all volume settings less than -96 db are equivalent to muting the channel via the atapi bits (see section 4.8.3). 76543210 volx7 volx6 volx5 volx4 volx3 volx2 volx1 volx0 00000000
cs44210 16 ds539pp1 note: all volume settings greater than +18 db are interpreted as +18 db. 4.4 tone control (address 05h) 4.4.1 bass boost level (bb) default = 0 db (no bass boost) function: the level of the shelving bass boost filter is set by bass boost level. the level can be adjusted in 1 db increments from 0 to +12 db of boost. boost levels are decoded as shown in table 3. levels above +12 db are interpreted as +12 db. 4.4.2 treble boost level (tb) default = 0 db (no treble boost) function: the level of the shelving treble boost filter is set by treble boost level. the level can be adjusted in 1 db increments from 0 to +12 db of boost. boost levels are decoded as shown in table 4. levels above +12 db are interpreted as +12 db. note: treble boost is not available in double speed mode. binary code decimal value volume setting 00001010 12 +12 db 00000111 7 +7 db 00000000 0 0 db 11000100 -60 -60 db 10100110 -90 -90 db table 2. example volume settings 76543210 bb3 bb2 bb1 bb0 tb3 tb2 tb1 tb0 00000000 binary code decimal value boost setting 0000 0 0 db 0010 2 +2 db 1010 6 +6 db 1001 9 +9 db 1100 12 +12 db table 3. example bass boost settings binary code decimal value boost setting 0000 0 0 db 0010 2 +2 db 1010 6 +6 db 1001 9 +9 db 1100 12 +12 db table 4. example treble boost settings
cs44210 ds539pp1 17 4.5 mode control 1 (address 06h) 4.5.1 bass boost corner frequency (bbcf) default = 00 00 - 50 hz 01 - 100 hz 10 - 200 hz 11 - reserved function: the bass boost corner frequency is user-selectable. the corner frequency is a function of lrck (sam- pling frequency), the dbs bit and the bbcf bits as shown in table 5 and table 6. 4.5.2 treble boost corner frequency (tbcf) default = 00 00 - 2 khz 01 - 4 khz 10 - 7 khz 11 - reserved function: the treble boost corner frequency is user selectable. the corner frequency is a function of lrck (sam- pling frequency) and the tbcf bits as shown in table 7. note: treble boost is not available in double speed mode. 76543210 bbcf1 bbcf0 tbcf1 tbcf0 tc1 tc0 tc_en lim_en 00000000 bbcf fs lrck in single speed mode (dbs=0) 48 khz 24 khz 12 khz 8 khz 00 50 hz 25 hz 12.5 hz 8.33 hz 01 100 hz 50 hz 25 hz 16.7 hz 10 200 hz 100 hz 50 hz 33.3 hz 11 reserved reserved reserved reserved table 5. base boost corner frequencies in single speed mode bbcf fs lrck in double speed mode (dbs=1) 96 khz 48 khz 24 khz 16 khz 00 50 hz 25 hz 12.5 hz 8.33 hz 01 100 hz 50 hz 25 hz 16.7 hz 10 200 hz 100 hz 50 hz 33.3 hz 11 reserved reserved reserved reserved table 6. base boost corner frequencies in double speed mode
cs44210 18 ds539pp1 4.5.3 tone control mode (tc) default = 00 00 - all settings are taken from user registers 01 - 12 db of bass boost at 100 hz and 6 db of treble boost at 7 khz (at lrck = 48 khz) 10 - 8 db of bass boost at 100 hz and 4 db of treble boost at 7 khz (at lrck = 48 khz) 11 - 4 db of bass boost at 100 hz and 2 db of treble boost at 7 khz (at lrck = 48 khz) function: the tone control mode bits determine how the bass boost and treble boost features are configured. the user-defined settings from the bass and treble boost level and corner frequency registers are used when these bits are set to ? 00 ? . alternately, one of three pre-defined settings may be used (these settings are a function of lrck - refer to tables 5, 6, and 7). note: treble boost is not available in double speed mode. 4.5.4 tone control enable (tc_en) default = 0 0 - disabled 1 - enabled function: the bass boost and treble boost features are active when this function is enabled. 4.5.5 peak signal limiter enable (lim_en) default = 0 0 - disabled 1 - enabled function: the cs44210 will limit the maximum signal amplitude to prevent clipping when this function is enabled. peak signal limiting is performed by first decreasing the bass and treble boost levels. if the signal is still clipping, the digital attenuation is increased. the attack rate is determined by the limiter attack rate register. once the signal has dropped below the clipping level, the attenuation is decreased back to the user se- lected level followed by the bass boost being increased back to the user selected level. the release rate is determined by the limiter release rate register. note: the a=b bit should be set to ? 1 ? for optimal limiter performance. tbcf fs lrck in single speed mode (dbs=0) 48 khz 24 khz 12 khz 8 khz 00 2 khz 1 khz 0.5 khz 0.33 khz 01 4 khz 2 khz 1 khz 0.67 khz 10 7 khz 3.5 khz 1.75 khz 1.17 khz 11 reserved reserved reserved reserved table 7. treble boost corner frequencies in single speed mode
cs44210 ds539pp1 19 4.6 limiter attack rate (address 07h) (arate) default = 10h - 2 lrck?s per 1/8 db function: the limiter attack rate is user-selectable. the rate is a function of sampling frequency, as, and the value in the limiter attack rate register. rates are calculated using the function rate = 32/{value}, where {val- ue} is the decimal value in the limiter attack rate register and rate is in lrck ? s per 1/8 db of change. note: a value of zero in this register is not recommended, as it will induce erratic behavior of the limiter. use the lim_en bit to disable the limiter function (see "peak signal limiter enable (lim_en)" ). 4.7 limiter release rate (address 08h) (rrate) default = 20h - 16 lrck ? s per 1/8 db function: the limiter release rate is user-selectable. the rate is a function of sampling frequency, fs, and the value in the limiter release rate register. rates are calculated using the function rate = 512/{value}, where {value} is the decimal value in the limiter release rate register and rate is in lrck ? s per 1/8 db of change. note: a value of zero in this register is not recommended, as it will induce erratic behavior of the limiter. use the lim_en bit to disable the limiter function (see "peak signal limiter enable (lim_en)" ). 76543210 arate7 arate6 arate5 arate4 arate3 arate2 arate1 arate0 00010000 binary code decimal value lrck ? s per 1/8 db 00000001 1 32 00010100 20 1.6 00101000 40 0.8 00111100 60 0.53 01011010 90 0.356 table 8. example limiter attack rate settings 76543210 rrate7 rrate6 rrate5 rrate4 rrate3 rrate2 rrate1 rrate0 00100000 binary code decimal value lrck ? s per 1/8 db 00000001 1 512 00010100 20 25 00101000 40 12 00111100 60 8 01011010 90 5 table 9. example limiter release rate settings
cs44210 20 ds539pp1 4.8 volume and mixing control (address 09h) 4.8.1 input mux selection (is) default = 00 00 - selects sdin1 as input 01 - selects sdin2 as input 10 - selects sdin3 as input 11 - reserved function: the input mux selector determines which sdin input is selected. 4.8.2 ramp speed (rmp_sp) default = 01 00 - ramp speed = approximately 0.1 seconds 01 - ramp speed = approximately 0.2 seconds 10 - ramp speed = approximately 0.3 seconds 11 - ramp speed = approximately 0.65 seconds function: this feature is used in single ended applications to reduce pops in the output caused by the dc-blocking capacitor. when in control port mode, the ramp speed sets the time for the pwm signal to linearly ramp up and down from the bias point (50% pwm duty cycle). refer to section 6.4. 4.8.3 atapi channel mixing and muting (atapi) default = 1001 - hp_a = l, hp_b = r (stereo) function: the cs44210 implements the channel mixing functions of the atapi cd-rom specification. refer to table 10 and figure 6 for additional information. note: all mixing functions occur prior to the digital volume control. 76543210 is1 is0 rmp_sp1 rmp_sp0 atapi3 atapi2 atapi1 atapi0 00001001
cs44210 ds539pp1 21 atapi3 atapi2 atapi1 atapi0 hp_a hp_b 0000 mute mute 0001 mute r 0010 mute l 0011 mute [(l+r)/2] 0100 r mute 0101 r r 0110 r l 0111 r [(l+r)/2] 1000 l mute 1001 l r 1010 l l 1011 l [(l+r)/2] 1100[(l+r)/2] mute 1101[(l+r)/2] r 1110[(l+r)/2] l 1111[(l+r)/2] [(l+r)/2] table 10. atapi decode hp_a hp_b left channel audio data right channel audio data channel b digital volume control eq channel a digital volume control eq & mute & mute figure 6. dynamics control block diagram
cs44210 22 ds539pp1 4.9 mode control 2 (address 0ah) 4.9.1 master clock divide enable (mclkdiv) default = 0 function: the mclkdiv bit enables a circuit which divides the externally applied mclk signal by 2 prior to all other internal circuitry. mclkdiv, dbs, clkdiv and frqsft are set per the user ? s mclk and lrck require- ments. refer to tables 11, 12, 13, 14, and section 6.2. 4.9.2 clock divide (clkdiv) default = 00 function: mclkdiv, dbs, clkdiv and frqsft are set per the user ? s mclk and lrck requirements. refer to tables 11, 12, 13, 14, and section 6.2 . 4.9.3 double speed mode (dbs) default = 0 0 - single speed 1 - double speed (dbs) function: single speed supports 8khz to 50 khz sample rates and double speed supports 50 khz to 96khz sample rates. mclkdiv, dbs, clkdiv and frqsft are set per the user ? s mclk and lrck requirements. refer to tables 11, 12, 13, 14, and section 6.2. note: de-emphasis, ramp control, and treble control are not available in double speed mode. 4.9.4 frequency shift (frqsft) default = 00 function: mclkdiv, dbs, clkdiv and frqsft are set per the user ? s mclk and lrck requirements. refer to tables 11, 12, 13, 14, and section 6.2. 76543210 mclkdiv clkdv1 clkdv0 dbs frqsft1 frqsft0 dem1 dem0 00000000
cs44210 ds539pp1 23 dbs = 0 mclkdiv = 0 dbs = 0 mclkdiv = 1 lrck (khz) mclk/ lrck mclk (mhz) mclk/ lrck mclk (mhz) frqsft1 frqsft0 clkdiv1 clkdiv0 pwm switching freq. (khz) 48 256 12.288 512 24.576 0 0 0 0 48 384 18.432 768 36.864 0 0 0 1 384 48 512 24.576 1024 49.152 0 0 1 0 44.1 256 11.2896 512 22.5792 0 0 0 0 44.1 384 16.9344 768 33.8688 0 0 0 1 352.8 44.1 512 22.5792 1024 45.1584 0 0 1 0 32 512 16.384 1024 32.768 0 1 0 0 32 768 24.576 1536 49.152 0 1 0 1 512 32 1024 32.768 2048 65.536 0 1 1 0 24 512 12.288 1024 24.576 0 1 0 0 24 768 18.432 1536 36.864 0 1 0 1 384 24 1024 24.576 2048 49.152 0 1 1 0 12 1024 12.288 2048 24.576 1 0 0 0 12 1536 18.432 3072 36.864 1 0 0 1 384 12 2048 24.576 4096 49.152 1 0 1 0 8 1536 12.288 3072 24.576 1 1 0 0 8 2304 18.432 4608 36.864 1 1 0 1 384 8 3072 24.576 6144 49.152 1 1 1 0 table 11. single speed clock modes - control port mode lrck (khz) mclk/ lrck mclk (mhz) pwm switching freq. (khz) 48 256 12.288 48 384 18.432 384 48 512 24.576 44.1 256 11.2896 44.1 384 16.9344 352.8 44.1 512 22.5792 32 1024 32.768 512 24 1024 24.576 12 2048 24.576 8 1536 12.288 384 8 2304 18.432 8 3072 24.576 table 12. single speed clock modes - stand-alone mode
cs44210 24 ds539pp1 4.9.5 de-emphasis control (dem) default = 00 00 - disabled 01 - 44.1 khz 10 - 48 khz 11 - 32 khz function: selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter re- sponse at 32, 44.1 or 48 khz sample rates (see figure 7). note: de-emphasis is not available in double speed mode . dbs = 1 mclkdiv = 0 dbs = 1 mclkdiv = 1 lrck (khz) mclk/ lrck mclk (mhz) mclk/ lrck mclk (mhz) frqsft1 frqsft0 clkdiv1 clkdiv0 pwm switching freq. (khz) 9612812.28825624.5760000 9619218.43238436.8640001384 9625624.57651249.1520010 table 13. double speed clock modes - control port mode lrck (khz) mclk/ lrck mclk (mhz) pwm switching freq. (khz) 96 128 12.288 384 96 192 18.432 table 14. double speed clock modes - stand-alone mode gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 7. de-emphasis curve
cs44210 ds539pp1 25 4.10 mode control 3 (address 0bh) 4.10.1 digital interface formats (dif) default = 00 00 - i 2 s 01 - right justified, 16 bit 10 - left justified 11 - right justified, 24 bit function: the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed in figures 19 through 22. 4.10.2 channel a volume = channel b volume (a=b) default = 0 0 - disabled 1 - enabled function: the hp_a and hp_b volume levels and the driver_x outputs are independently controlled by the a and the b channel volume control bytes when this function is disabled. the volume on both hp_a, hp_b, driver_a and driver_b are determined by the a channel volume control byte and the b channel byte is ignored when this function is enabled. 4.10.3 volume control bypass (vcbyp) default = 0 0 - disabled 1 - enabled function: the digital volume control section is bypassed when this function is enabled. this disables the digital vol- ume control, muting, bass boost, treble boost, limiting, and atapi functions. 4.10.4 control port enable (cp_en) default = 0 0 - disabled 1 - enabled function: this bit defaults to 0, allowing the device to power-up in stand-alone mode. the control port mode can be accessed by setting this bit to 1. this will allow the operation of the device to be controlled by the reg- isters and the pin definitions will conform to control port mode. refer to section 7.1 . 76543210 dif1 dif0 a=b vcbyp cp_en freeze hpsen reserved 00000000
cs44210 26 ds539pp1 4.10.5 freeze (freeze) default = 0 0 - disabled 1 - enabled function: this function allows modifications to be made to the registers without the changes being taking effect until the freeze is disabled. to make multiple changes in the control port registers take effect simultaneous- ly, you will first enable the freeze bit, then make all register changes, then disable the freeze bit. 4.11 revision indicator (address 0ch)[read only] default = none 0000 - revision a 0001 - revision b 0010 - revision c etc. function: this read-only register indicates the revision level of the device. 76543210 reserved reserved reserved reserved rev3 rev2 rev1 rev0 00000000
cs44210 ds539pp1 27 5. pin description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 24 23 22 21 20 19 18 17 16 15 serial data 2 sdin2 sdin3 serial data 3 serial data 1 sdin1 rst reset left/right clock lrck gnd headphone b ground serial clock sclk hp_b headphone b output master clock mclk va_hpb headphone b power digital power vd va_hpa headphone a power ground gnd hp_a headphone a output interface power vl gnd headphone a ground scl/cclk/dif0 scl/cclk/dif0 sda/cdin/dem sda/cdin/dem addr0/chipsel /dif1 ad0/cs /dif1 ad1/cdout addr1/cdout sync clock sync_clk driver_a driver output a test in tstin driver_b driveroutput b sdin1 sdin2 sdin3 2 1 24 serial audio data input ( input ) - input for two ? s complement serial audio data. unused inputs should be grounded. lrck 3 left right clock ( input ) - determines which channel, left or right, is currently active on the serial audio data line. the frequency of the left/right clock must be at the audio sample rate, fs. sclk 4 serial clock ( input ) - serial clock for the serial audio interface. mclk 5 master clock ( input ) - clock source for the pwm modulator and digital filters. table 11, 12, 13 and 14 illustrate several sta ndard audio sample rates and the required master clock frequen- cies. vd 6 digital power ( input ) - positive power supply for the digital section. refer to "recommended operating conditions" for appropriate voltages. gnd 7, 17 & 22 ground ( input ) - ground reference. vl 8 logic power ( input ) - determines the required signal level for the digital input/output. refer to "recommended operating conditions" for appropriate voltages. sync clock 11 sync_clk ( output) - provides a high frequency clock signal at 32 x pwm switching frequency to synchronize external circuitry, if needed. tstin 12 test in ( input) - this pin is not used and must remaing floating. driver_a driver_b 14 13 driver outputs ( outputs) outputs used to drive external power devices. hp_a hp_b 18 21 headphone outputs ( output ) - pwm headphone outputs. an external lc filter should be added to suppress high frequency switching noise. a dc blocking capacitor is also required. refer to typical connection diagrams. va_hpa va_hpb 19 20 headphone amplifier power ( input ) - positive power supply for the headphone amplifier. refer to "recommended operating conditions" for appropriate voltages. rst 23 reset ( input ) - the device enters a low power mode and all internal registers are reset to their default settings when low. the control port cannot be accessed when reset is low. see sec- tion 6.5 control port definitions scl/cclk 9 serial control port clock ( input ) - serial clock for the serial control port. requires an external pull-up resistor to vl in two-wire mode.
cs44210 28 ds539pp1 ado/cs 10 address bit 0 (two-wire) / control port chip select (spi) ( input ) - ad0 is a chip address pin two-wire mode; cs is used to enable the control port interface. ad1/cdout 15 ad1/cdout - address bit 1 (two wire) / serial control data out (spi) ( input/output ) - in two- wire mode, ad1 is a chip address pin. in spi mode, cdout is the output data from the control port interface. sda/cdin 16 serial control data ( input/output ) - sda is a data i/o line in two-wire mode and requires an external pull-up resistor to the logic interface voltage. cdin is the input data line for the control port interface in spi mode. stand alone definitions dif0 dif1 9 10 digital interface format (i nput ) - the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed below ad1/cdout 15 non-applicable (input) - non-functional in this mode should be connected to ground. dem 16 de-emphasis control ( input ) - selects the standard 15 s/50 s digital de-emphasis filter response at 44.1 khz sample rates. note: de-emphasis is not available in double or quad speed modes. when dem is grounded, de-emphasis is disabled. . dif1 dif0 description figure 0 0 left justified, up to 24-bit data 19 0 1 right justified, 24 -bit data 20 10i 2 s, up to 24-bit data 21 1 1 right justified, 16-bit data 22 table 15. digital interface format - dif1 and dif0 (st d al m d )
cs44210 ds539pp1 29 6. applications 6.1 grounding and power supply decoupling as with any switching converter, the cs44210 re- quires careful attention to power supply and grounding arrangements to optimize performance. figures 4 and 5 show the recommended power ar- rangement with vd, va_hpx, and vl connected to clean supplies. decoupling capacitors should be located as close to the device package as possible. if desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be used on each supply pin. 6.2 clock modes one of the characteristics of a pwm amplifier is that the frequency content of out-of-band noise generated by the modulator is dependent on the pwm switching frequency. the systems designer will specify the external filter based on this switch- ing frequency. the obvious implementation in a digital pwm system is to directly lock the pwm switching rate to the incoming data sample rate. however, this would require a tuneable filter to at- tentuate the switching frequency across the range of possible sample rates. to simplify the external filter design and to accommodate sample rates ranging from 8 khz to 96 khz the cs44210 con- troller uses several clock modes that keep the pwm switching frequency in a small range. in control port mode, for operation at a particular sample rate the user selects register settings (refer to section 4.9 and tables 11 and 13) based on their mclk and mclk/lrck parameters. when us- ing stand-alone mode, refer to tables 12 and 14 for available clock modes. 6.3 de-emphasis the cs44210 includes on-chip digital de-empha- sis. figure 7 shows the de-emphasis curve. the fre- quency response of the de-emphasis curve will scale proportionally with changes in sample rate, fs. the de-emphasis feature is included to accommo- date older audio recordings that utilize pre-empha- sis equalization as a means of noise reduction. 6.4 pwm popguard transient control the cs44210 uses popguard ? technology to mini- mize the effects of output transients during pow- er-up and power-down. this technique minimizes the audio transients commonly produced by sin- gle-ended, single-supply converters when it is im- plemented with external dc-blocking capacitors connected in series with the audio outputs. when the device is initially powered-up, the driver_x, and hp_x outputs are clamped to gnd. following a delay each output begins to in- crease the pwm duty cycle toward the quiescent voltage point. by a speed set by the rmp_sp bit, the driver_x and hp_x outputs will later reach the bias point (50% pwm duty cycle), and audio output begins. this gradual voltage ramping allows time for the external dc-blocking capacitor to charge to the quiescent voltage, minimizing the power-up transient. to prevent transients at power-down, the device must first enter its power-down state. when this oc- curs, audio output ceases and the pwm duty cycle is decreased until the driver_x and hp_x out- puts reach gnd. the time required to reach gnd is determined by the rmp_sp bits. this allows the dc-blocking capacitors to slowly discharge. once this charge is dissipated, the power to the device may be turned off, and the system is ready for the next power-on. to prevent an audio transient at the next power-on, the dc-blocking capacitors must fully discharge before turning off the power or exiting the pow- er-down state. if full discharge does not occur, a transient will occur when the audio outputs are ini- tially clamped to gnd. the time that the device must remain in the power-down state is related to the value of the dc-blocking capacitance and the output load. for example, with a 220 f capacitor
cs44210 30 ds539pp1 and a 16 ohm load on the headphone outputs, the minimum power-down time will be approximately 0.4 seconds. note that ramp up and ramp down period can be set to zero with the rupbyp and rdnbyp bits re- spectively. 6.5 recommended power-up sequence 6.5.1 stand alone mode 1. hold rst low until the power supply, master, and left/right clocks are stable. in this state, the control port is reset to its default settings and the hp_x and driver_x lines will remain low. 2. bring rst high. the device will remain in a low power state and will initiate the stand-alone pow- er-up sequence. the control port will be accessible at this time. 6.5.2 control port mode 1. hold rst low until the power supply, master, and left/right clocks are stable. in this state, the control port is reset to its default settings and the hp_x and driver_x lines will remain low. 2. bring rst high. the device will remain in a low power state and will initiate the stand-alone pow- er-up sequence. the control port will be accessible at this time. 3. on the cs44210 the control port pins are shared with stand-alone configuration pins. to enable the control port, the user must set the cp_en bit. this is done by performing a two-wire or spi write. once the control port is enabled, these pins are ded- icated to control port functionality. to prevent audible artifacts the cp_en bit (see section 4.10.4) should be set prior to the comple- tion of the stand-alone power-up sequence, ap- proximately 21ms. writing this bit will halt the stand-alone power-up sequence and initialize the control port to its default settings. note, the cp_en bit can be set any time after rst goes high; how- ever, setting this bit after the stand-alone pow- er-up sequence has completed can cause audible artifacts.
cs44210 ds539pp1 31 7. control port interface the control port is used to load all the internal set- tings. the operation of the control port may be completely asynchronous with the audio sample rate. however, to avoid potential interference prob- lems, the control port pins should remain static if no operation is required. the cs44210 has map auto increment capability, enabled by the incr bit in the map register, which is the msb. if incr is 0, then the map will stay constant for successive writes. if incr is set to 1, then map will auto increment after each byte is written, allowing block reads or writes of succes- sive registers. 7.1 format selection the control port has 2 formats: spi and two-wire, with the cs44210 operating as a slave device. if two-wire operation is desired, ad0/cs should be tied to vl or gnd. if the cs44210 ever detects a high to low transition on ad0/cs after power-up and after the control port is activated, spi format will be selected. 7.2 two-wire format in two-wire format, sda is a bidirectional data line. data is clocked into and out of the part by the clock, scl, with a clock to data relationship as shown in figure 8. the receiving device should send an acknowledge (ack) after each byte re- ceived. there is no cs pin. pins ad0 and ad1 forms the partial chip address and should be tied to vl or gnd as required. the upper 6 bits of the 7- bit address field must be 001000. note: mclk is required during all two-wire transactions. the two-wire format is compatible with the i 2 c protocol. 7.2.1 writing in two-wire format to communicate with the cs44210, initiate a start condition of the bus. next, send the chip address. the eighth bit of the address byte is the r/w bit (low for a write). the next byte is the memory address pointer, map, which selects the register to be read or written. the map is then fol- lowed by the data to be written. to write multiple registers, continue providing a clock and data, waiting for the cs44210 to acknowledge between each byte. to end the transaction, send a stop condition. 7.2.2 reading in two-wire format to communicate with the cs44210, initiate a start condition of the bus. next, send the chip address. the eighth bit of the address byte is the r/w bit (high for a read). the contents of the reg- ister pointed to by the map will be output after the chip address. to read multiple registers, continue providing a clock and issue an ack after each byte. to end the transaction, send a stop condi- tion. 7.3 spi format in spi format, cs is the cs44210 chip select sig- nal, cclk is the control port bit clock, cdin is the input data line from the microcontroller, cdout is the output data line, and the chip address is 0010000. cs , cclk and cdin are all inputs and data is clocked in on the rising edge of cclk. cd- out is an output and is three-stated when not ac- tively outputting data. 7.3.1 writing in spi figure 9 shows the operation of the control port in spi format. to write to a register, bring cs low. the first 7 bits on cdin form the chip address and must be 0010000. the eighth bit is a read/write in- dicator (r/w ), which must be low to write. the next 8 bits form the memory address pointer (map), which is set to the address of the register that is to be updated. the next 8 bits are the data which will be placed into register designated by the map. to write multiple registers, keep cs low and continue providing clocks on cclk. end the read transaction by setting cs high.
cs44210 32 ds539pp1 sda scl 001000 addr ad0 r/w start ack data 1-8 ack data 1-8 ack stop note: if operation is a write, this byte contains the memory address pointer, map. note 1 figure 8. control port timing, two-wire format map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 0010000 figure 9. control port timing, spi format (write)
cs44210 ds539pp1 33 7.3.2 reading in spi figure 10 shows the operation of the control port in spi format. to read to a register, bring cs low. the first 7 bits on cdin form the chip address and must be 0010000. the eighth bit is a read/write indicator (r/w ), which must be high to read. the cdout line will then output the data from the register des- ignated by the map. to read multiple registers, keep cs low and continue providing clocks on cclk. end the read transaction by setting cs high. the cdout line will tri-state once cs goes high. 7.4 memory address pointer (map) 7.4.1 incr (auto map increment enable) default = ? 0 ? 0 - disabled 1 - enabled 7.4.2 map3-0 (memory address pointer) default = ? 0000 ? lsb byte 1 byte n r/w address chip cdin cclk cs 0010000 msb data cdout figure 10. control port timing, spi format (read) 76543210 incr reserved reserved reserved map3 map2 map1 map0 00000000
cs44210 34 ds539pp1 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 0.10.20.30.40.50.60.70.80.9 1 frequency (norm alized to fs) amplitude (db) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 frequency (normalized to fs) amplitude (db) figure 11. single speed stopband rejection figure 12. single speed transition band -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0. 45 0. 46 0. 47 0. 48 0. 49 0. 5 0. 51 0. 52 0. 53 0. 54 0. 55 frequency (norm alized to fs) amplitude (db) -0.5 -0.4 -0.3 -0.2 -0.1 0 0. 1 0. 2 0. 3 0. 4 0. 5 0 0. 05 0. 1 0. 15 0. 2 0. 25 0. 3 0.35 0. 4 0. 45 0. 5 frequency (norm alized to fs) amplitude (db) figure 13. single speed transition band (detail) figure 14. single speed passband ripple -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (normalized to fs) amplitude (db) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 frequency (normalized to fs) amplitude (db) figure 15. double speed stopband rejection figure 16. double speed transition band
cs44210 ds539pp1 35 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0. 45 0. 46 0. 47 0. 48 0. 49 0. 5 0.51 0. 52 0. 53 0.54 0. 55 frequency (normalized to fs) amplitude (db) -0.50 -0.40 -0.30 -0.20 -0.10 0.00 0.10 0.20 0.30 0.40 0.50 0. 00 0.05 0. 10 0. 15 0. 20 0.25 0.30 0. 35 0. 40 0. 45 0.50 f requency (normalized to f s ) figure 17. double speed transition band (detail) figure 18. double speed passband ripple figure 19. left justified, up to 24-bit data lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 figure 20. right justified, 24-bit data lrck sclk left channel sdata 6543210 7 23 22 21 20 19 18 6543210 7 23 22 21 20 19 18 32 clocks 0 right channel lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 figure 21. i 2 s, up to 24-bit data
cs44210 36 ds539pp1 8. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering so- ciety, aes17-1991, and the electronic industries association of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right channels. measured for each channel at the converter ? s output with all zeros to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. 9.0 references 1) ?the i 2 c-bus specification: version 2.0? philips semiconductors, december 1998. http://www.semiconductors.philips.com figure 22. right justified, 16-bit data lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 32 clocks
cs44210 ds539pp1 37 10. package dimensions note: 1. ? d ? and ? e1 ? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2.dimension ? b ? does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ? b ? dimension at maximum material condition. dambar intrusion shall not reduce dimension ? b ? by more than 0.07 mm at least material condition. 3.these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.043 -- -- 1.10 a1 0.002 0.004 0.006 0.05 -- 0.15 a2 0.03346 0.0354 0.037 0.85 0.90 0.95 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.303 0.307 0.311 7.70 7.80 7.90 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- 0.026 bsc -- -- 0.65 bsc -- l 0.020 0.024 0.028 0.50 0.60 0.70 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters. 24l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view

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